As the density of integrated circuits, such as dynamic random access memory (DRAM) devices, has increased, the size of the contact hole for connecting to a metal layer has decreased while the aspect ratio of the contact hole has increased. As a result, the fabrication of contact structures for sub-micron complementary metal oxide semiconductor (CMOS) devices is difficult. Typically, a contact structure is formed after the formation of the capacitor elements. However, if the contact structure can be formed before the formation of the capacitor structure and withstand the high temperature steps required in the formation of the capacitor structure(s), the process flow can be simplified and a reduced aspect ratio for the contact hole(s) can be obtained.
A need has been felt for a technique for forming a contact with a diffusion barrier which is easy to fabricate, which results in low contact resistance, and which has sufficient thermal stability to withstand the process temperature required in the formation of capacitor elements.